In this paper, an area efficient method is presented to design and implement FIR filter. The proposed FIR filter has been implemented equiripple window using Transposed & Symmetric structure. The performance of two designs has been compared in terms of hardware requirements. The performance of both the designs is almost same but the Symmetric structure has shown reduced hardware requirement as compared to Transposed structure. The proposed designs have been designed and simulated using Matlab 7.0. The Symmetric FIR filter has shown 55% reduction in multipliers as compared to Transposed structure for FIR filters.
The Direct form transposed FIR filter produces the same output as the Direct form FIR but the cost varies in terms hardware requirements of Direct form Symmetric FIR. The difference is that it performs all the multiplications of a variable at the same time. The design time is also a key factor for low price products which is shown in implementation cost.
The proposed FIR filter architecture is capable of operating for 16 bits word length filter coefficient. We show that dynamically reconfigurable filters can be efficiently implemented by using Direct form Symmetric FIR structure for equiripple FIR filter.
Hence, an efficient design process aiming at high speed and great interest for minimizing the total cost
Keywords: DSP, FIR, MAC, FPGA